This invention relates to field isolation structures and to methods of forming field isolation structures.
In semiconductor wafer fabrication, isolation of adjacent devices has often been accomplished by forming thick oxide regions between the adjacent devices using a local oxidation of silicon method (often referred to as LOCOS) or by forming trench isolation regions between the adjacent devices. As critical dimensions get smaller and smaller in ever increasing density geometries, the width of the isolation regions formed between adjacent devices has decreased. Accordingly, the isolation effect provided by such isolation regions has also decreased. At some point, the isolation is decreased enough that the potential of source-drain regions of adjacent devices, which are electrically isolated by such isolation regions, begins to be adversely effected. For example, as the degree of isolation decreases, the threshold/turn-on voltages of adjacent devices may be effected, adversely impacting the operation of such devices.
Methods exist wherein conductively doped polysilicon is deposited within isolation trenches as isolation material. In one such process, a trench is formed within a bulk substrate, and then the sidewalls and base of the trench are thermally oxidized. After the oxidation has been completed, the base of the trench is etched, and then conductively doped polysilicon is deposited within the trench as isolation material. In another such process, the base of the trench is not etched, and the conductively doped polysilicon is deposited over the oxide which covers the base of the trench.
Although such methods of forming trench isolation regions are useful, such methods also have shortcomings. For example, when the conductively doped polysilicon is provided by deposition, the processing generally requires an additional step wherein excess polysilicon which has been formed outside the trench is removed. Additionally, when conductively doped polysilicon is provided within a trench to form an isolation region between an n-type region and a p-type region, due to non-ideal PN junction formation, current leakage tends to occur between the n-type region and the p-type region.
The present invention was principally motivated in overcoming the above identified issues. However, the invention is in no way so limited, and is only limited by the accompanying claims as literally worded and appropriately interpreted in accordance with the Doctrine of Equivalents.
Field isolation structures and methods of forming field isolation structures are described. In one implementation, a method includes etching a trench within a monocrystalline silicon substrate. The trench has sidewalls and a base, with the base comprising monocrystalline silicon. A dielectric material is formed on the sidewalls of the trench. Epitaxial monocrystalline silicon is grown from the base of the trench and over at least a portion of the dielectric, material. An insulating layer is formed over the epitaxial monocrystalline silicon.
According to one implementation, the invention includes a field isolation structure formed within a semiconductor substrate. The field isolation structure includes a monocrystalline silicon comprising substrate. A trench having sidewalls is formed within the monocrystalline silicon comprising substrate. A dielectric material is received on the sidewalls within the trench. Monocrystalline silicon is received within the trench between the dielectric material of the sidewalls. An insulating layer is received over the monocrystalline silicon within the trench.